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1/25 october 2005 STM6717/6718/6719/6720 stm6777/6778/6779*/6780* dual/triple ultra-low voltage supervisors with push-button reset (with delay option) rev 3.0 * contact local st sales office for availability. features summary primary supply (v cc1 ) monitor. fixed (factory-programmed) reset thresholds: 4.63v to 1.58v secondary supply (v cc2 ) monitor (STM6717/18/19/20/77/78). fixed (factory-programmed) reset thresholds: 3.08v to 0.79v tertiary supply monitor (using externally adjustable rstin): 0.626v internal reference rst outputs (push-pull or open drain); state guaranteed if v cc1 or v cc2 0.8v reset delay time (t rec ) on power-up: ?210ms (typ) manual reset input (mr ) optional delayed manual reset input (mrc) with external capacitor (stm6777/78/79/80) low supply current - 11a (typ), v cc1 = v cc2 = 3.6v operating temperature: ?40c to 85c (industrial grade) figure 1. packages table 1. device options sot23-5 (wy) sot23-6 (wb) part number monitored voltages manual reset input (mr ) delayed mr pin (mrc) reset output (rst ) package v cc1 v cc2 rstin active-low (push-pull) active-low (open drain) STM6717 ?? ? ? wy stm6718 ?? ? ? wy stm6719 ??? ? ? wb stm6720 ??? ? ? wb stm6777 ?? ? ? ? wb stm6778 ?? ? ? ? wb stm6779* ???? ? wb stm6780* ????? wb
STM6717/6718/6719/ 6720/6777/6778/6779*/6780* 2/25 table of contents features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 1. packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 1. device options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 summary description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 2. logic diagram (STM6717/18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3. logic diagram (stm6719/20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 4. logic diagram (stm6777/78) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 5. logic diagram (stm6779/80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 2. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 6. STM6717/18 sot23-5 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 7. stm6719/20 sot23-6 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 8. stm6777/78 sot23-6 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 9. stm6779/80 sot23-6 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 10.block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 11.hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 12.stm67xx interface to processor with bi-directional reset pins . . . . . . . . . . . . . . . . . . . . 8 figure 13.ensuring rst valid to v cc = 0 (active-low, push-pull outputs) . . . . . . . . . . . . . . . . . . . 8 typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 14.supply current vs. temperature (v cc1 = 5.5v; v cc2 = 3.6v). . . . . . . . . . . . . . . . . . . . . . 9 figure 15.supply current vs. temperature (v cc1 = 3.6v; v cc2 = 2.75v). . . . . . . . . . . . . . . . . . . . . 9 figure 16.supply current vs. temperature (v cc1 = 3.0v; v cc2 = 2.0v). . . . . . . . . . . . . . . . . . . . . 10 figure 17.supply current vs. temperature (v cc1 = 2.0v; v cc2 = 1.0v). . . . . . . . . . . . . . . . . . . . . 10 figure 18.normalized v cc reset time-out period vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . 11 figure 19.maximum v cc transient duration vs. reset threshold overdrive . . . . . . . . . . . . . . . . . 11 figure 20.normalized v rst1 threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 21.normalized v rst2 threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 22.reset input threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 23.v cc1 -to-reset delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 24.reset input-to-reset output delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 25.mr -to-reset output delay vs. temperature (v cc1 = 3.6v) . . . . . . . . . . . . . . . . . . . . . . 14 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 5. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3/25 STM6717/6718/6719/6720/ 6777/6778/6779*/6780* figure 26.ac testing input/output waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 27.mr timing waveform (STM6717/18/19/20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 28.mr timing waveform (stm6777/78/79/80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 6. dc and ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 7. t mlmh minimum pulse width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 29.sot23-5 ? 5-lead small outline transistor package mechanical drawing . . . . . . . . . . 21 table 8. sot23-5 ? 5-lead small outline transistor package mechanical data . . . . . . . . . . . . . 21 figure 30.sot23-6 ? 6-lead small outline transistor package mechanical drawing . . . . . . . . . . 22 table 9. sot23-6 ? 6-lead small outline transistor package mechanical data . . . . . . . . . . . . . 22 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 10. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 11. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
STM6717/6718/6719/ 6720/6777/6778/6779*/6780* 4/25 summary description the STM6717/18/19/20 and stm6777/78/79/80 supervisors are a family of low voltage/low supply current processor (micro or dsp) supervisors, de- signed to monitor two (o r three) system power supply voltages. they are targeted at applications such as set-top boxes (stbs), portable, battery- powered systems, networking, and communica- tion systems. all device options have a push-button-type manu- al reset input (mr ). the stm6777/78/79/80 also includes an option which enables the user to delay the start of the manual reset process from 6s (mrc pin left open) or more with external capaci- tor. the delay is implemented by connecting the appropriately sized capacitor between the mrc pin and v ss (typical 4s delay with a 3.3f capaci- tor, see table 7., page 19 ). two of the three supplies monitored (v cc1 and v cc2 ) have fixed (customer-selectable, factory- trimmed) thresholds (v rst1 and v rst2 ). the third voltage is monitored using an externally adjust- able rstin threshold (0.626v internal reference). if any of the three monitored voltages drop below its factory-trimmed or adjustable thresholds, or if mr is asserted to logic low, a rst is asserted (driven low). once asserted, rst is maintained at low for a minimum delay period (t rec ) after all supplies rise above their respective thresholds and mr returns to high. these devices are guar- anteed to be in the correct reset output logic state when v cc1 and/or v cc2 is greater than 0.8v. these devices are available in a standard 5-pin or 6-pin sot23 packages (see table 1., page 1 ). figure 2. logic diagram (STM6717/18) figure 3. logic diagram (stm6719/20) figure 4. logic diagram (stm6777/78) figure 5. logic diagram (stm6779/80) ai10413 v cc1 STM6717 stm6718 v ss v cc2 rst mr ai10414 v cc1 stm6719 stm6720 v ss v cc2 rst rstin mr ai10415 v cc1 stm6777 stm6778 v ss v cc2 rst mrc mr ai10416 v cc stm6779 stm6780 v ss rst mrc rstin mr
5/25 STM6717/6718/6719/6720/ 6777/6778/6779*/6780* table 2. signal names figure 6. STM6717/18 sot23-5 connections figure 7. stm6719/20 sot23-6 connections figure 8. stm6777/78 sot23-6 connections figure 9. stm6779/80 sot23-6 connections mr push-button reset input mrc manual reset delay input rst active-low reset output v cc1 primary supply voltage input v cc2 secondary supply voltage input rstin adjustable reset comparator input v ss ground 1 rst v cc1 v cc2 mr v ss ai10417 2 3 4 5 1 rst v cc1 v cc2 mr v ss ai10419 2 3 4 6 5 rstin 1 rst v cc1 v cc2 mr v ss ai10418 2 3 4 5 6 mrc 1 rst v cc1 mrc mr v ss ai10420 2 3 4 6 5 rstin
STM6717/6718/6719/ 6720/6777/6778/6779*/6780* 6/25 pin descriptions active-low, push-pull reset output (rst ) - stm6718/20/78/80. the rst pin is driven low and stays low whenever v cc1 or v cc2 or rstin falls below its factory-trimmed or adjustable reset threshold or when mr goes to logic low. it remains low for t rec after all supply voltages being moni- tored rise above their reset thresholds and mr goes from low to high. (push-pull outputs are ref- erenced to v cc1 .) active-low, open drain reset output (rst ) - STM6717/19/77/79. the rst pin is driven low and stays low whenever v cc1 or v cc2 or rstin falls below its factory-trimmed or adjustable reset threshold or when mr goes to logic low. it remains low for t rec after all supply voltages being moni- tored rise above their reset thresholds and mr goes from low to high. connect an external pull-up resistor to v cc1 . a 10k ? pull-up resistor should be sufficient for most applications. push-button reset input (mr ). when mr goes low the rst output is driven low. rst remains low as long as mr is low and for t rec after mr returns to high. this active-low input has an internal 50k ? pull-up resistor to v cc1 . it can be driven from a ttl or cmos logic line, or with open drain/collec- tor outputs, or connected to v ss through a switch. if unused, leave this pin open or connect it to v cc1 . connect a normally open momentary switch from mr to v ss ; external debounce circuitry is not re- quired. (if mr is driven from long cables or if the device is used in noisy environments, connecting a 0.1f capacitor from mr to v ss provides addi- tional noise immunity. manual reset delay input (mrc) - stm6777/78/ 79/80). this pin is either left open or connected to v ss via a capacitor. by selecting the appropriate capacitor, the manual reset process, initiated by pressing the push-button manual reset input, can be delayed by any value from 6s or more (see table 7., page 19 ). primary supply voltage monitoring input (v cc1 ). it also is the input for the primary reset threshold monitor. available fixed (customer-se- lectable, factory-programmed) reset thresholds in- clude 4.63v to 1.58v. secondary supply voltage monitoring input (v cc2 ). this function is available on the STM6717/18/19/20/77/78. fixed (customer-se- lectable, factory-programmed) reset thresholds in- clude 3.08v to 0.79v. adjustable reset comparator input (rstin; stm6719/20/79/80). this is a high impedance in- put. rst is driven low when the voltage at the rstin pin falls below 0.626v (internal reference voltage at this comparator). the monitored voltage reset threshold is set with an external resistor-di- vider network. table 3. pin functions pin name function STM6717 stm6718 stm6719 stm6720 stm6777 stm6778 stm6779 stm6780 1111rst active-low reset output 3333mr push-button reset input ? ? 5 4 mrc manual reset delay input 5666 v cc1 primary supply voltage input 444? v cc2 secondary supply voltage input ? 5 ? 5 rstin adjustable reset comparator input 2222 v ss ground
7/25 STM6717/6718/6719/6720/ 6777/6778/6779*/6780* figure 10. block diagram note: 1. v cc2 input is available on STM6717/18/19/20/77/78. 2. rstin available only on stm6719/20/79/80. 3. mrc available only on stm6777/78/79/80. figure 11. hardware hookup note: 1. v cc2 is available only on STM6717/18/19/20/77/78. 2. rstin available only on stm6719/20/79/80. 3. mrc available only on stm6777/78/79/80. ai10421 v ref/2 = 0.626 rst compare compare compare logic t rec generator rstin (2) v cc2 (1) v cc1 v rst2 v rst1 mr mrc (3) v cc1 ai10422 v cc1 v cc2 v ss v cc1 mr mrc (3) 0.1 f stm67xx rstin (2) rst rst (to processor reset) push-button switch c r1 from dc/dc converter r2 v cc2 (1) v cc3 0.1 f v cc3 = (626.5mv) ( r1 + r2 r2 )
STM6717/6718/6719/ 6720/6777/6778/6779*/6780* 8/25 operation applications information 1. interfacing to processors with bi-directional reset pins most processors with bi-directional reset pins can interface directly to the open drain rst outputs (STM6717/19/77/79). systems simultaneously requiring a push-pull rst output and a bi-directional reset interface can be in logic contention. to prevent this contention, connect a 4.7k ? resistor between rst and the processor?s reset i/o as shown in figure 12. 2. ensuring a valid rst output down to v cc =0v the stm67xx supervisors are guaranteed to be in the correct rst output logic state when v cc1 and/or v cc2 is greater than 0.8v. in applications which require valid reset levels down to v cc = 0, a pull-down resistor to active-low outputs (push-pull only, see figure 13. ) will ensure that the reset line is valid while the reset output can no longer sink or source current. this scheme does not work with the open drain outputs of the STM6717/19/77/79. the resistor value used is not critical, but it must be large enough not to load the reset output when v cc is above the reset threshold. for most applications, 100k ? is adequate. figure 12. stm67xx interface to processor with bi-directional reset pins figure 13. ensuring rst valid to v cc = 0 (active-low, push-pull outputs) ai10425 v cc1 v cc2 v ss v cc1 stm67xx rst to other system components 4.7k ? v cc2 v ss processor reset ai10426 v cc1 v cc1 v ss stm67xx rst r1
9/25 STM6717/6718/6719/6720/ 6777/6778/6779*/6780* typical operating characteristics note: typical values are at t a = 25c unless otherwise noted. figure 14. supply current vs. temperature (v cc1 = 5.5v; v cc2 = 3.6v) figure 15. supply current vs. temperature (v cc1 = 3.6v; v cc2 = 2.75v) i cc1 i cc2 i total 0 2 4 6 8 10 12 14 16 18 ?40 ?20 0 20 40 60 80 temperature ( c) supply current (a) ai11843 i cc1 i cc2 i total 0 2 4 6 8 10 12 14 16 18 ?40 ?20 0 20 40 60 80 temperature ( c) supply current (a) ai11844
STM6717/6718/6719/ 6720/6777/6778/6779*/6780* 10/25 figure 16. supply current vs. temperature (v cc1 = 3.0v; v cc2 = 2.0v) figure 17. supply current vs. temperature (v cc1 = 2.0v; v cc2 = 1.0v) 0 ai11845 2 4 6 8 10 12 14 16 18 ?40 ?20 0 20 40 60 80 temperature ( c) supply current (a) i cc1 i cc2 i total 0 ai11846 2 4 6 8 10 12 14 16 18 ?40 ?20 0 20 40 60 80 temperature ( c) supply current (a) i cc1 i cc2 i total
11/25 STM6717/6718/6719/6720/ 6777/6778/6779*/6780* figure 18. normalized v cc reset time-out period vs. temperature figure 19. maximum v cc transient duration vs. reset threshold overdrive 0.97 ai11847 0.99 1.01 1.03 1.05 1.07 ?40 ?20 0 20 40 60 80 temperature ( c) reset period 1 ai11848 10 100 1000 1 10 100 1000 reset threshold overdrive (mv) maximum v cc transient duration (s)
STM6717/6718/6719/ 6720/6777/6778/6779*/6780* 12/25 figure 20. normalized v rst1 threshold vs. temperature figure 21. normalized v rst2 threshold vs. temperature 0.996 ai11849 0.998 1.000 1.002 1.004 ?40 ?20 0 20 40 60 80 temperature ( c) v rst1 reset threshold 0.996 ai11850 0.998 1.000 1.002 1.004 ?40 ?20 0 20 40 60 80 temperature ( c) v rst2 reset threshold
13/25 STM6717/6718/6719/6720/ 6777/6778/6779*/6780* figure 22. reset input threshold vs. temperature figure 23. v cc1 -to-reset delay vs. temperature 624 ai11851 625 626 627 628 629 630 ?40 ?20 0 20 40 60 80 temperature ( c) reset input threshold (mv) 28 32 36 40 44 48 ?40 ?20 0 20 40 60 80 temperature ( c) v cc1 -to-reset delay (s) ai11852
STM6717/6718/6719/ 6720/6777/6778/6779*/6780* 14/25 figure 24. reset input-to-reset output delay vs. temperature figure 25. mr -to-reset output delay vs. temperature (v cc1 = 3.6v) 25.0 ai11853 25.5 26.0 26.5 27.0 27.5 28.0 28.5 29.0 ?40 ?20 0 20 40 60 80 temperature ( c) rstin-to-reset output delay (s) 400 ai11854 420 440 460 480 500 ?40 ?20 0 20 40 60 80 temperature ( c) mr-to-reset output delay (ns)
15/25 STM6717/6718/6719/6720/ 6777/6778/6779*/6780* maximum rating stressing the device above the rating listed in the absolute maximum ratings? table may cause per- manent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im- plied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 4. absolute maximum ratings note: 1. reflow at peak temperature of 255c to 260c for < 30 seconds (total thermal budget not to exceed 180c for between 90 t o 150 seconds). symbol parameter value unit t stg storage temperature (v cc off) ?55 to 150 c t sld (1) lead solder temperature for 10 seconds 260 c v io input or output voltage ?0.3 to v cc1 + 0.3 v ?0.3 to v cc2 + 0.3 v v cc1, v cc2 supply voltage ?0.3 to 7.0 v i io input or output current (all pins) 20 ma p d power dissipation sot23-5 654 mw sot23-6 675 mw
STM6717/6718/6719/ 6720/6777/6778/6779*/6780* 16/25 dc and ac parameters this section summarizes the operating measure- ment conditions, and the dc and ac characteris- tics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 5. , operating and ac measurement conditions. designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. table 5. operating and ac measurement conditions figure 26. ac testing input/output waveforms figure 27. mr timing waveform (STM6717/18/19/20) figure 28. mr timing waveform (stm6777/78/79/80) note: 1. by connecting a certain capacitor between the mrc pin and v ss , the rst can be delayed from 6s or more (t mlmh , see table 7., page 19 ). parameter stm67xx unit v cc supply voltage 0.8 to 5.5 v ambient operating temperature (t a ) ?40 to 85 c input rise and fall times 5ns input pulse voltages 0.2 to 0.8v cc v input and output timing ref. voltages 0.3 to 0.7v cc v ai02568 0.8v cc 0.2v cc 0.7v cc 0.3v cc ai10423a rst mr tmlrl trec tmlmh ai10424c rst mr trec tmlmh (1) tmlrl
17/25 STM6717/6718/6719/6720/ 6777/6778/6779*/6780* table 6. dc and ac characteristics sym alter- native description test condition (1) min typ max unit v cc operating voltage 0.8 5.5 v i cc1 v cc1 supply current v cc1 < 5.5v, all i/o pins open 12 35 a v cc1 < 3.6v, all i/o pins open 823a i cc2 v cc2 supply current v cc2 < 3.6v, all i/o pins open 39a v cc2 < 2.75v, all i/o pins open 2.5 7 a i li (2) input leakage current 0v = v in = v cc ?1 +1 a i lo open drain rst output leakage current v cc1 > v rst1 , v cc2 > v rst2 ; rst not asserted 0.5 a v ol output low voltage (rst ; push-pull or open drain) v cc1 or v cc2 0.8v, i sink = 1a, rs t asserted 0.3 v v cc1 or v cc2 1.0v, i sink = 50a, rs t asserted 0.3 v v cc1 or v cc2 1.2v, i sink = 100a, rst asserted 0.3 v v cc1 or v cc2 2.7v, i sink = 1.2ma, rst asserted 0.3 v v cc1 or v cc2 4.5v, i sink = 3.2ma, rst asserted 0.4 v v oh output high voltage (rst ; push-pull only) v cc1 1.8v, i source = 200a, rst not asserted 0.8v cc1 v v cc1 2.7v, i source = 500a, rst not asserted 0.8v cc1 v v cc1 4.5v, i source = 800a, rst not asserted 0.8v cc1 v t r (3) push-pull rst rise time (stm6718/20/78/80) rise time measured from 10% to 90% of v cc ; c l = 5pf, v cc = 3.3v 525ns reset thresholds v rst1 (4) v th1 v cc1 reset threshold l (falling) 4.500 4.625 4.750 v m (falling) 4.250 4.375 4.500 v t (falling) 3.000 3.075 3.150 v s (falling) 2.850 2.925 3.000 v r (falling) 2.550 2.625 2.700 v z (falling) 2.250 2.313 2.375 v y (falling) 2.125 2.188 2.250 v w (falling) 1.620 1.665 1.710 v v (falling) 1.530 1.575 1.620 v
STM6717/6718/6719/ 6720/6777/6778/6779*/6780* 18/25 v rst2 (4) v th2 v cc2 reset threshold t (falling) 3.000 3.075 3.150 v s (falling) 2.850 2.925 3.000 v r (falling) 2.550 2.625 2.700 v z (falling) 2.250 2.313 2.375 v y (falling) 2.125 2.188 2.250 v w (falling) 1.620 1.665 1.710 v v (falling) 1.530 1.575 1.620 v i (falling) 1.350 1.388 1.425 v h (falling) 1.275 1.313 1.350 v g (falling) 1.080 1.110 1.140 v f (falling) 1.020 1.050 1.080 v k (falling) 0.895 0.925 0.955 v j (falling) 0.845 0.875 0.905 v e (falling) 0.810 0.833 0.855 v d (falling) 0.765 0.788 0.810 v v hyst reset threshold hysteresis referenced to v rst typical 0.5 % t rd v cc to rst delay v cc1 = (v rst1 + 100mv) to (v rst ? 100mv) 20 s v cc2 = (v rst2 + 75mv) to (v rst2 ? 75mv) 20 s t rec t rp rst time-out period 140 210 280 ms adjustable reset comparator input (stm6719/20/79/80) v rstin rstin input threshold 611 626.5 642 mv i rstin rstin input current ?25 +25 na rstin hysteresis 3 mv t rstind rstin to rst output delay v rstin to (v rstin ? 30mv) 22 s sym alter- native description test condition (1) min typ max unit
19/25 STM6717/6718/6719/6720/ 6777/6778/6779*/6780* note: 1. valid for ambient operating temperature: t a = ?40 to 85c; v cc1 = 0.8 to 5.5v and v cc2 = 0.8 to 3.6v (except where noted). 2. input leakage for the mrc pin is not tested. 3. guaranteed by design. 4. the leakage current measured on the rst pin is tested with the reset de-asserted (output high impedance). 5. selecting the appropriate external capacitor (preferably less than 100pf) allows systems designers to vary the minimum delay from 6s (mrc pin left open) or more (see table 7. ). table 7. t mlmh minimum pulse width note: 1. at 25c (typical) manual (push-button) reset input v il mr input voltage 0.3v cc1 v v ih 0.7v cc1 v t mlmh t mr mr minimum pulse width (STM6717/18/19/20) 1s mr minimum pulse width (stm6777/78/79/80) mrc connected via capacitor to v ss (5) 6s t mlrl t mrd mr to rst output delay 200 ns mr glitch immunity (STM6717/18/19/20) 100 ns mr pull-up resistance 25 50 80 k ? v cc1 capacitor value (1) 100pf 0.1f 2.2f 3.3f 4.7f 6.8f 1.6v 120s 120ms 2.6s 4.0s 5.6s 8.2s 2.0v 122s 122ms 2.7s 4.0s 5.8s 8.3s 3.0v 125s 125ms 2.7s 4.1s 5.9s 8.5s 4.0v 128s 129ms 2.8s 4.2s 6.0s 8.7s 5.0v 130s 130ms 2.8s 4.3s 6.1s 8.8s sym alter- native description test condition (1) min typ max unit
STM6717/6718/6719/ 6720/6777/6778/6779*/6780* 20/25 package mechanical in order to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specif ications are avail able at: www.st.com.
21/25 STM6717/6718/6719/6720/ 6777/6778/6779*/6780* figure 29. sot23-5 ? 5-lead small outline transistor package mechanical drawing note: drawing is not to scale. table 8. sot23-5 ? 5-lead small outline transistor package mechanical data note: dimensions per jedec sot/sop product outline mo-178c, variation aa symb mm inches typ min max typ min max a ? ?1.45? ?0.057 a1 ? ? 0.15 ? ? 0.006 a2 1.15 0.90 1.30 0.045 0.035 0.051 b ? 0.30 0.50 ? 0.012 0.020 c ? 0.08 0.22 ? 0.003 0.009 d 2.90 ? ? 0.114 ? ? e 2.80 ? ? 0.110 ? ? e1 1.60 ? ? 0.063 ? ? e0.95? ?0.037? ? e1 1.90 ? ? 0.075 ? ? l 0.45 0.30 0.60 0.018 0.012 0.024 4 0 8 4 0 8 n5 5 sot23-5b c 0.10 a a2 a1 5x c d e1 e e a m cab 5x b 0.20 1 b e1 c l datum a 0.20
STM6717/6718/6719/ 6720/6777/6778/6779*/6780* 22/25 figure 30. sot23-6 ? 6-lead small outline transistor package mechanical drawing note: drawing is not to scale. table 9. sot23-6 ? 6-lead small outline transistor package mechanical data note: dimensions per jedec sot/sop product outline mo-178c, variation aa symb mm inches typ min max typ min max a ? ?1.45? ?0.057 a1??0.15??0.006 a2 1.15 0.90 1.30 0.045 0.035 0.051 b ? 0.30 0.50 ? 0.012 0.020 c ? 0.08 0.22 ? 0.003 0.009 d 2.90 ? ? 0.114 ? ? e 2.80 ? ? 0.110 ? ? e1 1.60 ? ? 0.063 ? ? e0.95? ?0.037? ? e1 1.90 ? ? 0.075 ? ? l 0.45 0.30 0.60 0.018 0.012 0.024 4 0 8 4 0 8 n6 6 sot23-6 e1 d e 6x b e a m 0.10 c a b 1 0.10 c a a2 a1 6x c b e1 c datum a 0.20 l
23/25 STM6717/6718/6719/6720/ 6777/6778/6779*/6780* part numbering table 10. ordering information scheme note: 1. these are standard versions and are typically held in stock. a non-standard version may require a higher minimum volumes , and/ or longer delivery times. for other options, or for more information on any aspect of this device, please contact the st sales office nearest you. 2. contact local st sales office for availability. example: stm67xx lt wy 6 e device type stm67xx reset thresholds (v rst1 and v rst2 ) for v cc1 and v cc2 STM6717/18/19/20/77/78 (v rst1 and v rst2 ) suffix v rst1 v rst2 lt 4.625 3.075 ms 4.375 2.925 mr 4.375 2.625 tz (1) 3.075 2.313 tw (1) 3.075 1.665 ti 3.075 1.388 tg (1) 3.075 1.110 tk 3.075 0.925 te 3.075 0.833 sy (1) 2.925 2.188 sv (1) 2.925 1.575 sh 2.925 1.313 sf (1) 2.925 1.050 sj 2.925 0.875 sd 2.925 0.788 yv 2.188 1.575 yh 2.188 1.313 yf 2.188 1.050 yj 2.188 0.875 yd 2.188 0.788 vh 1.575 1.313 vf 1.575 1.050 vj 1.575 0.875 vd 1.575 0.788 stm6779/80 (v rst1 only) (2) l? 4.625 ? t? 3.075 ? s? 2.925 ? y? 2.188 ? v? 1.575 ? r? 2.625 ? z? 2.313 ? package wy = sot23-5 wb = sot23-6 temperature range 6 = ?40 to 85c shipping method e = ecopack package, tubes f = ecopack package, tape & reel
STM6717/6718/6719/ 6720/6777/6778/6779*/6780* 24/25 revision history table 11. document revision history date version revision details 18-october-04 1.0 first draft 25-oct-04 1.1 descriptive text, sales types (table 10 ) 14-jan-05 1.2 update characteristics, pin functions (table 3 ) 09-feb-05 1.3 update characteristics (figure 10 ; table 3 ) 08-apr-05 1.4 update characteristics and mechanical dimensions; add table (figure 10 , 11 , 28 , 29 , 30 ; table 4 , 6 , 10 , 8 , 9 ) 28-jul-05 1.5 updated characteristics, reset delay (figure 11 , 28 ; table 4 , 6 , 7 , 10 ) 13-sep-05 2.0 add operating characteristics; update timings, document status, lead-free text (figure 14 , 15 , 16 , 17 , 18 , 19 , 20 , 21 , 22 , 23 , 24 , 25 , 27 , 28 ; table 10 ) 07-oct-05 3.0 marked stm6779/6780 as availability request parts (table 1 , 10 )
25/25 STM6717/6718/6719/6720/ 6777/6778/6779*/6780* information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2005 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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